Grid optimization for maximum power output of large-area organic solar cells

Perovskite and organic semiconductors are suitable for cheap mass-production of large-area solar modules and LEDs. These materials can be processed via solution and can be deposited at low temperatures. This could reduce, for example, the cost of the production of a solar cell and open new opportunities for their usage, such as in indoor IoT applications.

Unfortunately, the good performance of these solar cells and LEDs at the lab-scale decreases substantially for large-area devices.

The sheet resistance (Rs) of the transparent conductive oxide (TCO) layer is one of the factors contributing to the decrease in performance with the scale-up. The TCO is an optically transparent layer and provides a conformal electrical contact between the photoactive layer (layer emitting or absorbing light) and the electrode. The indium tin oxide (ITO) is a typical TCO material with an Rs on the order of 10 Ω/□, but for large-area production, it must be <1 Ω/□.

The question we want to answer in this blog is: how do you retain the efficiency of a lab-scale optimized solar cell when scaling up to large-area devices?

Recent publications from Burwell et al.[Bur20][Bur21] demonstrated how the addition of metallic grids on the TCO helps to preserve the performance of organic LEDs and solar cells by decreasing the total Rs.

The presence of an opaque metallic grid reduces the amount of photoactive area. Therefore, a compromise among shape, thickness, and width of the grid must be found, to guarantee scalability and adequate performance.

In this tutorial, we are showing how to optimize the geometry of a grid deposited on the TCO of a large-area (25 cm2) organic solar cell for maximum power output. We will use the simulation software Laoss, which is a FEM-solver to model large-area OLEDs and solar cells, but also displays and PV modules.

Electrical, Thermal, and Optical simulations are all possible with Laoss.

Device area, Rs, and performance

First: why do size and sheet resistance affect the performance of both solar cells and LEDs so much? The resistance can be written as:

where:

The drop in FF correlates with the quality of the voltage distribution within the device. In Table 1 one can observe the negative effect of increasing size (from left to right) and increasing Rs (from top to bottom) on the voltage distribution at the Maximum Power Point (VMPP) for devices with a voltage bias applied at the top and the bottom edge of the device layout.

In addition to an evident decrease in VMPP, the voltage distribution becomes less and less homogenous with size and Rs. A larger part of the device operates at a higher voltage than VMPP, hence it produces a lower amount of power.

Reducing Rs with a metallic grid

A TCO with a metallic grid added on top acts as resistances in parallel. Metals have lower resistivity than TCOs, hence they reduce the total Rs by adding a low-resistance parallel path for the current. . In this study, we considered a silver grid with a bulk resistivity of 1.59E-8 Ωm and a striped grid structure with stripes following the direction of the applied vertical bias.

Figure 2a is an example of the influence on the JV curve of a metallic grid with an increasing number of stripes for a 5x5 cm2 device with Rs=10 Ω/□. The grid has a fixed stripe width of 200 µm and the number of stripes is swept from 3 to 50 in steps of 3. With more stripes, the FF and VMPP improve at the expense of the total device current. More specifically, the improvement has a logarithmic behavior with an initial sharp increase quickly followed by a plateau (Figure 2b). On the other hand, the short circuit current shows a linearly decreasing trend with the increase of grid stripes, due to the reduction of the photoactive area (Figure 2c orange line). Because of the opposite trend of VMPP and I, the power per area (Figure 2c blue line) has its peak at about 9 stripes followed by a constant decrease when more grid stripes are added.

Whilst the analysis was made only considering metal stripes, qualitatively similar conclusions would be obtained with other grid geometries.

How about varying the stripe width? Or the thickness of the grid? Or the grid geometry? Here is where Laoss could help you. Laoss features an optimization tool that allows you to find immediately the ideal grid dimensions based on your desired target and you can avoid comparisons of countless simulation results

With Laoss it is possible to find immediately the ideal grid dimensions based on your desired target thanks to the optimization tool and avoid comparisons of countless simulation results.

The best grid in a few clicks

In the following, we will show how the optimization tool works and how to set it up to obtain reliable results. The example below is limited to the striped geometry, but it applies to other grid geometries as well.

Laoss approximates the 3D solar cell device stack as a 2D+1D+2D system. The electrodes are modeled as 2D domains while the coupling law between the two electrodes is approximated by a 1D analytical or tabulated law.

In the present study, the coupling between the two electrodes is defined by importing an experimental JV curve of an organic solar cell with an area of 0.4 cm2 measured under illumination. [Bur21] For the metal grid, a JV curve measured in the dark is also imported.

In a standard busbar device measurement, the voltage bias is applied to the top electrode of the device, while the bottom one is grounded. To replicate these conditions in Laoss, and for a highly conductive bottom electrode, it is sufficient to select the single electrode mode (Figure 3). Equivalent conditions and, therefore, simulation results, can be obtained by choosing coupled electrodes and setting 0V at the bottom electrode.

For the ITO we considered an Rs =10 Ω/□ and for the metal grid an Rs = 0.016 Ω/□. In the boundary conditions, we selected opposite edges as the location where to apply the voltage bias sweep (see Figure 4). In this case, the bias is in the vertical direction and goes from -1 to 1 with a 0.05 V step.

After setting the desired range for the voltage sweep, it is possible to proceed with the configuration for the optimization. (Figure 5) The main settings to look at are:

• the optimization target (blue circle): the device parameter that we intend to maximize or minimize. In this example, we want to find the largest power per area. It entails optimizing for the minimum value since the current has a negative sign, due to convention;

• the optimization variables (green circle): what can be varied to reach the desired optimization target. Here the goal is to find the best grid for max power production, hence the variables will include stripe width and the total number of stripes;

• the optimization algorithm (gold circle): only local, or global and local. We advise you to choose the latter. Local optimizers alone are suitable only for a finer adjustment of the optimization variables when a reasonable starting value (initial guess in the software GUI) is already known. You can find more information on the various types of algorithms in the Laoss manual.

The quality of the final results depends on the number of iterations, but the process can become extremely time and power-demanding with a high number of iterations (>100 per algorithm). As a general rule: start with a low amount (≈50) and evaluate from the results if more iterations can be helpful. More optimization variables usually require more iterations. In our case, it was not worth having more than 100 iterations for each optimizer.

Results analysis

Our goal is to reduce the losses caused by the size increment of the device or, in other words, to have the highest power per area for a large-area device. To understand whether the optimized grid is effective, it follows that one should compare the performance and potential distribution of a large-size device with a grid to a small-size device without a grid. The latter has intrinsically lower ohmic losses thanks to the reduced dimensions.

As clear from equation (2), thicker grids lead to lower Rs. As can be observed in Figure 6a, the thickest grid of 10 µm (equivalent to an Rs of 0.00159 Ω/□) leads to the highest power per area. It follows that the grid should be as thick as possible to allow better performance, but thin enough to avoid issues with the fabrication process. We considered grids with an Rs of 0.0159 Ω/□ (equivalent to 1 µm thickness) since the power loss compared to an Rs of 0.00159 Ω/□ (equivalent to 10 µm thickness) is only about 3% (Figure 6b).

Figure 7 shows the voltage profile along the normalized length in the y-axis (direction of the applied bias) for organic solar cells with 0.01 cm2 and 25 cm2 without grid and 25 cm2 with an optimized grid. The simulated devices have ITO with Rs=10 Ω/□ and an Ag grid with Rs=0.0159 Ω/□. For the large area device without the grid, the voltage has a sharp gradient toward the center up to values close to the Voc. The presence of the grid does not eliminate the gradient, but drastically flattens the voltage profile, which is almost comparable to the profile of the small-area device. This result is obtained with a striped grid made of 29 stripes with a width of 43 µm.

Table 2 compares the JV parameters of the different devices. The power loss for the large area is caused by a reduction in FF with a consequent reduction in the voltage at the Maximum Power Point (table cells with orange background). The addition of the grid brings the power per area (P) of the 25 cm2 device close to the 0.01 cm2 device.

Besides a significant efficiency reduction, the device without the grid has large ohmic losses, which lead to increased local heating effects. These can additionally lead to accelerated degradation. Thus, it is not only important to care about optimized grids for efficiency enhancement, but also for improving module stability.

Conclusions

Increasing the area of a thin-film electronic device, such as an organic solar cell or a Light-Emitting Diode hampers the device performance due to increased resistance. The addition of a metallic grid compensates for the negative effects connected to the device area by reducing the ohmic losses, but it reduces the device area contributing to the device functionality (photoactive area). A compromise between photoactive area and performance must be determined.

The simulation software Laoss with its embedded optimizer feature can be instrumental in finding the best compromise with the desired grid geometry and material avoiding endless comparisons of simulations results.

References

[Bur20] Burwell et al., “Metal Grid Structures for Enhancing the Stability and Performance of Solution‐Processed Organic Light‐Emitting Diodes”, Adv. Electron. Mater., vol. 6, 2000732, 2020

[Bur21] Burwell et al., “Parameterization of Metallic Grids on Transparent Conductive Electrodes for the Scaling of Organic Solar Cells”, Adv. Electron. Mater., vol. 7, 2100192, 2021